Evaluation of the users value of salts against apple scab and powdery mildew for fruit production

The research was aimed at finding anti resistance strategies for Integrated fruit growing. As the salts tested may be approvable for organic farming, the trial results are also of value for the development of scab an mildew control strategies for organic fruit growing. As new fungicides are mainly unisite action fungicides, the problem of fungicide resistance development is becoming more important every year. Combining chemical fungicides, which is the best anti-resistance strategy, is not always possible or recommended in the case when the number of available chemical fungicides are limited or a reduction in fungicide use is asked for. Therefore the use of salts as an anti-resistance strategy was looked upon. The salts evaluated were K(HCO3), KH2PO3, KHPO4 and K2SiO3. When using these salts as an anti-resistance strategy the efficacy obtained when spraying the compounds alone was often to low to be used in rotation with chemical fungicides. Only with K(HCO3)2 a good efficacy can be observed in some years. The variation in efficacy with K(HCO3)2 observed is higher for powdery mildew. K(HCO3)2 can be considered as a ideal product for scab control in organic orchards at moments of low infection risk

Towards zero latency photonic switching in shared memory networks

Photonic networks-on-chip based on silicon photonics have been proposed to reduce latency and power consumption in future chip multi-core processors (CMP). However, high performance CMPs use a shared memory model which generates large numbers of short messages, creating high arbitration latency overhead for photonic switching networks. In this paper we explore techniques which intelligently use information from the memory hierarchy to predict communication in order to setup photonic circuits with reduced or eliminated arbitration latency. Firstly, we present a switch scheduling algorithm which arbitrates on a per memory transaction basis and holds open photonic circuits to exploit temporal locality. We show that this can reduce the average arbitration latency overhead by 60% and eliminate arbitration latency altogether for a signicant proportion of memory transactions. We then show how this technique can be applied to multiple-socket shared memory systems with low latency and energy consumption penalties. Finally, we present ideas and initial results to demonstrate that cache miss prediction could be used to set up photonic circuits for more complex memory transactions and main memory accesses

Inefficiencies in the Cache Hierarchy: A Sensitivity Study of Cacheline Size with Mobile Workloads

With the rising number of cores in mobile devices, the cache hierarchy in mobile application processors gets deeper, and the cache size gets bigger. However, the cacheline size remained relatively constant over the last decade in mobile application processors. In this work, we investigate whether the cacheline size in mobile application processors is due for a refresh, by looking at inefficiencies in the cache hierarchy which tend to be exacerbated when increasing the cacheline size: false sharing and cacheline utilization. Firstly, we look at false sharing, which is more likely to arise at larger cacheline sizes and can severely impact performance. False sharing occurs when non-shared data structures, mapped onto the same cacheline, are being accessed by threads running on different cores, causing avoidable invalidations and subsequent misses. False sharing has been found in various places such as scientific workloads and real applications. We find that whilst increasing the cacheline size does increase false sharing, it still is negligible when compared to known cases of false sharing in scientific workloads, due to the limited level of thread-level parallelism in mobile workloads. Secondly, we look at cacheline utilization which measures the number of bytes in a cacheline actually used by the processor. This effect has been investigated under various names for a multitude of server and desktop applications. As a low cacheline utilization implies that very little of the fetched cachelines was used by the processor, this causes waste in bandwidth and energy in moving data across the memory hierarchy. The energy cost associated with data movements is much higher compared to logic operations, increasing the need for cache efficiency, especially in the case of an energy-constrained platform like a mobile device. We find that the cacheline utilization of mobile workloads is low in general, decreasing when increasing the cacheline size. When increasing the cacheline size from 64 bytes to 128 bytes, the number of misses will be reduced by 10%-30%, depending on the workload. However, because of the low cacheline utilization, this more than doubles the amount of unused traffic to the L1 caches. Using the cacheline utilization as a metric in this way, illustrates an important point. If a change in cacheline size would only be assessed on its local effects, we find that this change in cacheline size will only have advantages as the miss rate decreases. However, at system level, this change will increase the stress on the bus and increase the amount of wasted energy due to unused traffic. Using cacheline utilization as a metric underscores the need for system-level research when changing characteristics of the cache hierarchy

Towards zero latency photonic switching in shared memory networks

Photonic networks-on-chip based on silicon photonics have been proposed to reduce latency and power consumption in future chip multi-core processors (CMP). However, high performance CMPs use a shared memory model which generates large numbers of short messages, creating high arbitration latency overhead for photonic switching networks. In this paper we explore techniques which intelligently use information from the memory hierarchy to predict communication in order to setup photonic circuits with reduced or eliminated arbitration latency. Firstly, we present a switch scheduling algorithm which arbitrates on a per memory transaction basis and holds open photonic circuits to exploit temporal locality. We show that this can reduce the average arbitration latency overhead by 60% and eliminate arbitration latency altogether for a signi cant proportion of memory transactions. We then show how this technique can be applied to multiple-socket shared memory systems with low latency and energy consumption penalties. Finally, we present ideas and initial results to demonstrate that cache miss prediction could be used to set up photonic circuits for more complex memory transactions and main memory accesses

What Happens in Vegas Stays on TripAdvisor? A Theory and Technique to Understand Narrativity in Consumer Reviews

Many consumers base their purchase decisions on online consumer reviews. An overlooked feature of these texts is their narrativity: the extent to which they tell a story. The authors construct a new theory of narrativity to link the narrative content and discourse of consumer reviews to consumer behavior. They also develop from scratch a computerized technique that reliably determines the degree of narrativity of 190,461 verbatim, online consumer reviews and validate the automated text analysis with two controlled experiments. More transporting (i.e., engaging) and persuasive reviews have better developed characters and events as well as more emotionally changing genres and dramatic event orders. This interdisciplinary, multimethod research should help future researchers (1) predict how narrativity affects consumers’ narrative transportation and persuasion, (2) measure the narrativity of large digital corpora of textual data, and (3) understand how this important linguistic feature varies along a continuum

Low Latency Scheduling Algorithm for Shared Memory Communications over Optical Networks

Optical Network on Chips (NoCs) based on silicon photonics have been proposed to reduce latency and power consumption in future chip multi-core processors (CMP). However, high performance CMPs use a shared memory model which generates large numbers of short messages, typically of the order of 8-256B. Messages of this length create high overhead for optical switching systems due to arbitration and switching times. Current schemes only start the arbitration process when the message arrives at the input buffer of the network. In this paper, we propose a scheme which intelligently uses the information from the memory controllers to schedule optical paths. We identified predictable patterns of messages associated with memory operations for a 32 core x86 system using the MESI coherency protocol. We used the first message of each pattern to open the optical paths which will be used by all subsequent messages thereby eliminating arbitration time for the latter. Without considering the initial request message, this scheme can therefore reduce the time of flight of a data message in the network by 29% and that of a control message by 67%. We demonstrate the benefits of this scheduling algorithm for applications in the PARSEC benchmark suite with overall average reductions in overhead latency per message, of 31.8% for the streamcluster benchmark and 70.6% for the swaptions benchmark

PosterVote:expanding the action repertoire for local political activism

Online and digital technologies support and extend the action repertoires of localized social movements. In this paper we examine the ways by which digital technologies can support ‘on-the-ground ’ activist communities in the development of social movements. After identifying some of the challenges of deploying conventional voting and consultation technologies for activism, we examine situated political action in local communities through the design and deployment of a low-cost community voting prototype, PosterVote. We deploy PosterVote in two case studies with two local community organizations identifying the features that supported or hindered grassroots democratic practices. Through interviews with these communities, we explore the design of situated voting systems to support grassroots democratic practices and participation within an ecology of social action. Author Keywords Democracy; activism; participation; e-votin